library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pipepc is
	generic
	(
		DATA_WIDTH	: natural  :=	32		
	);

	port
	(
		-- Input ports
		clk	: in  std_logic;
		clrn : in std_logic;
		wpc	: in std_logic;
		cen : in std_logic;
		npc : in std_logic_vector(DATA_WIDTH-1 downto 0);
		irqmaskpc : in std_logic;
		-- Output ports
		irqmaskf : out std_logic;
		pc : out std_logic_vector(DATA_WIDTH-1 downto 0)		
	);
end pipepc;

architecture rtl_pipepc of pipepc is
component lpm_dffe32
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		enable		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
end component;
component lpm_dffe1
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC ;
		enable		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC 
	);
end component;
signal aclr: std_logic;
begin
	aclr <= not clrn;
	npc2pc: lpm_dffe32 port map(
		aclr => aclr,
		clock => clk,
		data => npc,
		enable => wpc and cen,
		q => pc
	);
	irqmaskd_r: lpm_dffe1 port map(
		aclr => aclr,
		clock => clk,
		data => irqmaskpc,
		enable => cen,
		q => irqmaskf
	);
end rtl_pipepc;
